The present invention relates to a blocking oscillator converter with controlling logic system for the supply of an electrical apparatus. A primary winding of a transformer is connected in series with the path of a switching transistor to carry the current to be switched.
A D.C. voltage is obtained through rectification of the mains A.C. voltage supplied via two external supply connections. A secondary winding of the transformer is provided for the purpose of current supply of the electrical apparatus. A control electrode of the switching transistor is controlled by an output of a control circuit which is controlled by the rectified A.C. voltage as the actual value and by a nominal value circuit.
In the logic system, a starting circuit is provided for further control of the control electrode of the switching transistor. The control circuit is constructed such that its current supply is provided by means of a secondary winding of the transformer which contains a circuit serving the purpose of generating a control voltage. The circuit comprises an AGC amplifier and a circuit for pulse processing. Both the output of the control amplifier as well as the output of the pulse processing system is connected to one input of a pulse-duration modulator connected to the control electrode of the switching transistor and forming the output of the control circuit. A third input of the pulse duration modulator is connected with a current-voltage converter.
Such a blocking oscillator converter with controlling logic system is described in German No. OS 30 32 034, incorporated herein by reference. As further prior art, see "Funkschau" (1975), volume 5, pages 40-43; the book of Wuestehube titled "Combinatorial Logic System Parts" appeared in 1977--VDE publisher--see for example page 87-139; and Siemens "Combinatorial Logic System Part With the IS TDA 4600", page 7 and following, all incorporated herein by reference.
As is known, such a logic system has the task of supplying an electrical apparatus e.g. a television receiver, with stabilized and controlled operating voltages. The heart of such a logic system is therefore a control circuit whose final control element is a switching transistor such as a bipolar power transistor. In addition, a high operating frequency and a transformer adjusted to a high operating frequency is provided since generally an extensive isolation of the electrical apparatus which is to be supplied from the supply network is desirable. Such logic systems can be designed either according to synchronized operation or according to self-oscillating operation. The latter type of operation applies to a logic system with which the present invention is concerned and such as is also described in the German No. OS 30 32 034, incorporated herein by reference.
The basic circuit diagram corresponding to such a logic system is illustrated in FIG. 1, which is first discussed hereafter.
A npn-power transistor T serves as the final control element for the control circuit and, with its emitter collector path, is connected in series with the primary winding W.sub.p of a transformer Tr. With reference to FIG. 1 of the German No. OS 30 32 034, it can be determined that the DC voltage U.sub.p, serving for the operation of such a series connection, is obtained by means of a rectifier circuit operated by the AC mains, for example, a Gratz (full-wave) rectifier circuit system. In the case of the use of an npn-transistor T, its emitter is connected to reference potential (ground), the collector is connected to the primary winding W.sub.p of the transformer Tr, and the other end of the primary winding is connected to the supply potential U.sub.p delivered by the above-described (but not illustrated in the drawing) rectifier circuit. The emittercollector path of the switching transistor T is bridged by a capacitor C.sub.s. The capacitance C.sub.w illustrated in FIG. 1 and connected to the primary winding W.sub.p, by contrast, is of a parasitic nature. The switching transistor T is controlled at its base by the output portion of the control circuit RS, i.e., in the case of the embodiment according to FIG. 1, by a pulse duration modulator PDM.
An auxiliary winding W.sub.H of the transformer Tr serves as a sensor for the control circuit RS and is therefore connected, at one end, to the reference potential and, at the other end, to the input of the control circuit RS. An additional winding W.sub.s forms the actual secondary side of the transformer Tr. It serves the purpose of supplying a rectifier system GL whose output is provided for the supply of the electric apparatus R.sub.L by means of a DC voltage U.sub.s.
In the preferred embodiment of a blocking oscillator converter with a controlling logic system illustrated in FIG. 1, the control circuit RS, in addition to the already cited output circuit PDM designed in the form of a pulse duration modulator, contains two input circuits controlled by the auxiliary winding W.sub.H. The one input circuit RSE serves the purpose of control voltage generation and, via an AGC amplifier RV, releases a control signal U.sub.A for the output circuit PDM. The other input circuit IAB serves the purpose of pulse processing and delivers a signal U.sub.N to the output circuit PDM of the control circuit RS. Finally, a current-voltage converter SSW is provided which forms the actual value control of the control circuit and releases a voltage U.sub.Ip proportional to the primary current I.sub.P to the pulse duration modulator PDM.
The last-cited portions of the control circuits RS are likewise disclosed in German No. OS 30 32 034, incorporated herein by reference. They correspond to the control circuit illustrated therein in FIG. 3. The control voltage generation RSE is provided by the resistances R5 and R4 apparent from FIGS. 1 and 2. The pulse processor IAB consists of the zero-axis crossing identification apparent in FIG. 3 of the German OS and of the control logic connected to it. Finally, the pulse duration modulator PDM is provided by the trigger circuit indicated in German No. OS 30 32 034 with the portion of the control logic connecting to drive it.
Connected to an additional terminal of the control circuit RS is the operating voltage U.sub.B which serves the purpose of supplying the control circuit RS and through which the reference potential (ground) and the supply potential connected to the cited terminal is provided.
The time diagram corresponding to a circuit according to FIG. 1 present herein, i.e. the chronological behavior of the signals U.sub.H occurring in the control circuit RS (=the signal released by the transformer auxiliary winding W.sub.H for the control of the control circuit RS , U.sub.N (=the signal delivered by the pulse processing IAB), I.sub.p (=the current delivered by the transformer winding W.sub.p connected in series with the switching transistor T, and U.sub.Ip (=the actual value signal delivered by the current voltage converter SSW), is illustrated in FIG. 2.
As is apparent, the voltage U.sub.H, delivered by the transformer winding W.sub.H, with the zero-axis crossing (U.sub.H =0 V), delivers the information that the energy stored in the transformer Tr has flowed off and that a new loading cycle can commence - i.e. the switch provided by the transistor T can be closed. Via the pulse processing stage IAB this information is communicated to the pulse duration modulator PDM. The following applies: U.sub.N &lt;0 V.fwdarw.pulse start, U.sub.N &gt;0 V.fwdarw.no pulse start possible.
In addition, one obtains from the auxiliary voltage U.sub.H, delivered by the auxiliary winding W.sub.H of the transformer Tr with the aid of the control voltage generator RSE, a control voltage U.sub.R which is proportional to the secondary voltage U.sub.S. In the AGC amplifier RV the control voltage is compared with a reference (=nominal value). The difference between the control voltage U.sub.R and the reference (=deviation) is amplified by the AGC amplifier RV and the signal voltage U.sub.A at its output is communicated to the pulse duration modulator PDM which compares it with the signal U.sub.Ip of the current voltage converter SSW and opens the switch provided by the transistor T as soon as U.sub.Ip .gtoreq.U.sub.A. In this manner, the peak value I.sub.pmax of I.sub.p is corrected until the difference between U.sub.R and the reference voltage disappears. This signifies that U.sub.R, and hence U.sub.S, remain constant.
If, in the case of a blocking oscillator converter with controlling logic system of the described type, and more generally the initially defined type, an error occurs in the control voltage generator RSE or in the voltage supply of the control circuit RS, the result is that the voltage U.sub.p assumes impermissably high values. This can lead to a corresponding excess increase of the secondary voltage U.sub.S and hence possibly to destructions in the electrical apparatus R.sub.L loaded by the logic system. In order to provide a remedy in this case, in the patent application No. P 33 36 422.2, incorporated herein by reference, a design of a blocking oscillator converter with controlling logic system corresponding to the previously provided description is proposed in which additionally an interference elimination circuit, which is inactive in the case of proper operation of the control circuit RS, is provided which, in turn, is connected to a secondary winding of the transformer Tr e.g. by the auxiliary winding W.sub.H. It is designed such that, spontaneously with exceeding of a provided limit value by the current arising in the secondary winding, it disconnects the current commonly flowing via the switching transistor T on the primary winding W.sub.p. A favorable embodiment of such an interference elimination circuit is also described in greater detail therein.
In the case of this interference elimination circuit, the activation of the switching transistor T by the output of the control circuit RS due to the action of the activated interference elimination circuit is blocked. This occurs until the influence of the interference behavior activating the interference elimination circuit and e.g. brought about by a faulty function in the control circuit, has died down again or has been compensated in another manner. Then a cancellation of the blocking and hence the activation of the control of the switching transistor T by the control circuit RS again automatically takes place.
In the case of such a solution to the cited problem, the effect is that the individual control pulses for the switching transistor T are suppressed. However, this frequently leads to the result that the power dissipation, primarily in the switching transistor T, can become very great. Therefore, a solution to the above-described problem is desired to the extent that the power dissipation in the blocking oscillator converter with controlling logic system is substantially reduced. The present invention is concerned with this objective.